To provide a PLL circuit in which phase noises can be improved, a lock-up time can be quickened, the number of circuit elements can be sharply reduced, and power consumption can be sharply reduced.

A second 233.15MHz local oscillation frequency fvco generated by a voltage control oscillator(VCO) 11 is converted into a7/8 of the frequency by a frequency converter 12, further 1/85 frequency-divided by a main counter 13, and inputted as a 2.4MHz comparison frequency to a phase comparator 14 as the one input. Also, 19.20007 104MHz reference frequency fr generated by a reference oscillator (TCXO) 15 is 1/8 frequency-divided by a reference counter 16, and inputted as a 2.4MHz reference frequency to the phase comparator 14 as the other input. Then, the compared output of the phase comparator 14 is inputted to a voltage control oscillator 11 through a charge pump circuit 17 and a low-pass filter 18.