To output a reference frequency signal having no fluctuation, synchronized with the outputted clock, even when the frequency range of the clock is varied widely by putting a delay circuit equivalent to the phase delay time of a frequency divider to an input side and correcting it.
A delay circuit 1 is provided on an input side. The delay circuit 1 delays a reference frequency signal f(H-Sync signal) by a time obtained by adding time which is a half of the time corresponding to the maximum frequency signal of the clock for synchronizing the reference frequency signal (f) to the delay time of a frequency divider 4. A phase comparator 2 outputs a control signal to VCO 3, so that the phase of the reference frequency signal (f) delayed by the delay circuit 1 matches with that of a signal, which is frequency-divided by the frequency divider 4. The VCO 3 oscillates the signal of the frequency synchronized with the reference frequency signal (f) and outputs it as a clock. A logic circuit 5 synchronizes the reference frequency signal (f) with the clock outputted from VCO 3 and outputs a synchronized reference frequency signal f'(H-Sync).
ISHIKAWA MASAAKI
YASUJIMA HIDEKATSU
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