To provide a PLL synthesize which can considerably shorten a pull-in time at the time of intermittent operation.

A synthesizer is provided with a fixed frequency divider 5 which frequency-divides the output of a reference oscillator 4, and a detection circuit 16 in which a reset function is provided for a variable frequency divider 2 which frequency-divides the output of a voltage control oscillator 1 and which detects an initial phase difference signal from a phase compactor 13 at pull-on time at the time of the intermittent operation. In such a case, the fluency dividers 2 and 5 are reset in accordance with the phase advance and delay prior to synchronism convergence, frequency-dividing phases are made equal and a filter is provided for the post stage of a phase compactor. An initial phase difference signal is not transmitted to CP(charge pump) and PLL synchronism is executed only a phase comparison signal corresponding to the frequency difference from a state where the phases are arranged.