PURPOSE: To make it possible to obtain a PLL phase comparator which generates its output with its higher-harmonic component attenuated sufficiently by adding a 1st input signal whose phase has been delayed by dividing to each OR-ELSE output of a 2nd input signal whose phase has been advanced by dividing.

CONSTITUTION: Divider 1 divides input signal S10 by two at its rise and divider 2 divides signal S10 by two at its fall to generate an output lagging the output of divider 1; and divider 3 divides signal S20 by two at its rise and divider 4 divides signal S20 by two at its fall to generate an output leading the output of divider 3. Here, OR-ELSE circuits 5 and 6 are provided which process outputs of dividers 1 and 4, and 2 and 3 by OR-ELSE, and outputs of circuits 5 and 6 are added 7 together. Consequently, the higher-harmonic component of the output of a PLL phase comparator can sufficiently be attenuated.