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Patent Searching and Data


Title:
PLOTTING PROCESSOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2004126928
Kind Code:
A
Abstract:

To make a plurality of engines process simultaneously, if there is no context in the execution results of the plurality of engines, thereby significantly improving hardware acceleration effect.

A CPU 2 produces command lists CM1, CM3, on the basis of map data, and stores the lists in a memory 6. A first and a second graphics engines 3, 4 perform arithmetic processing based on the lists CM1, CM3, and stores a plotting result in a frame buffer 6a. At the same time, the CPU 2 produces command lists CM2, CM 4 based on new map data and stores the lists in the memory 6. An image output part 5 displays a map obtained from the plotting result on a monitor 9. At that time, the first and the second graphics engines 3, 4 read the lists CM2, CM4, perform image arithmetic processing, and store the plotting result in a frame buffer 6b. The image output part 5 displays a map obtained from the plotting result on the monitor 9. These steps are repeated, to display a car navigation map on the monitor 9.


Inventors:
IMAI TAKAAKI
NAKAMURA ATSUSHI
HAMAZAKI HIROYUKI
MIYAMOTO TAKASHI
OMURA KENICHIRO
SATO JUN
Application Number:
JP2002289928A
Publication Date:
April 22, 2004
Filing Date:
October 02, 2002
Export Citation:
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Assignee:
RENESAS TECH CORP
International Classes:
G06F9/38; G06T15/00; G06T17/05; (IPC1-7): G06T15/00; G06F9/38; G06T17/50
Attorney, Agent or Firm:
Yamato Tsutsui