Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
POLLING RESPONSE CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS5848549
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of interruption to a CPU and to reduce the load of CPU, by automatically returning EOT information to general polling with a channel incorporated type of communication controller.

CONSTITUTION: When a power supply non-applicated state or a busy state takes place in a CPU 21, a chained command train is prepared to generate a start I/O instruction. When a channel incorporated type of communication controller 23 receives a read command, the polling wait state is obtained and when the polling is received, it is discriminated whether the polling is specific polling (S-Poll) or a general polling (G-Foll). In case of the G-Poll, a channel end bit in status information and a device end bit are set for interruption. In case of the S-Poll, the device 23 adds the channel end bit to the device end bit to set a unit exception bit for the interruption.


Inventors:
SATOU YOSHISHIGE
Application Number:
JP14738181A
Publication Date:
March 22, 1983
Filing Date:
September 18, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
H04L29/08; G06F13/00; G06F13/12; (IPC1-7): G06F3/04; H04L11/00; H04L13/00
Attorney, Agent or Firm:
Koshiro Matsuoka