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Title:
POLYGONAL LINE APPROXIMATION CIRCUIT
Document Type and Number:
Japanese Patent JPS61203711
Kind Code:
A
Abstract:

PURPOSE: To simplify the gain setting and adjustment by using a signal limiter circuit, a subtraction circuit and an addition amplifier circuit so as to decide the gain between polygonal points by one resistor.

CONSTITUTION: Each polygonal line is formed by a circuit group each comprising a signal limiter circuit (30∼32), an impedance converting circuit (33∼36) and a subtraction circuit (37∼39). Each circuit group converts an input signal for each polygonal line and the gain is changed by varying a gain adjusting resistor (R1∼R4) between polygonal points in an adder amplifier circuit 61 for each converted voltage. Thus, the gain between optional polygonal points is decided by one gain adjusting resistor. Thus, the gain setting/adjustment is executed simply.


Inventors:
MIZUHARA HIROHISA
NISHIYAMA YUTAKA
Application Number:
JP4535285A
Publication Date:
September 09, 1986
Filing Date:
March 07, 1985
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01D3/02; G01K7/14; G05B1/02; H03F1/32; (IPC1-7): G01D3/02; G01K7/14; G05B1/02; H03F1/32
Attorney, Agent or Firm:
Hiroaki Tazawa



 
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