Title:
PORTABLE TERMINAL INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JP2784979
Kind Code:
B2
Abstract:
PURPOSE: To easily and quickly access a processor while suppressing the power consumption of a battery part by switching a gate circuit to the cut-off state at the time of connecting a main body process unit to the processor through an interface part.
CONSTITUTION: When a bidirectional gate circuit 36 is inserted to a bus line 35 between a central operation processing part (CPU) 33 and a storage part (RAM) 34 and the processor is connected to the main body processor unit through an interface part 32, the gate circuit 36 is switched to the cut-off state. Then, access from the CPU 33 in the processor to the RAM 34 is inhibited, and data in the RAM 34 is mapped in a CPU on the main body process unit side. Thus, the communication system conforming to conventional fixed procedures is unnecessary. Consequently, the speeding-up of data processings such as up-loading and down-loading of the main body process unit is enabled.
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Inventors:
ITOGA TOSHOSHI
Application Number:
JP4259993A
Publication Date:
August 13, 1998
Filing Date:
March 03, 1993
Export Citation:
Assignee:
SHAAPU KK
International Classes:
G06K19/07; G11C5/00; (IPC1-7): G06K19/07; G11C5/00
Domestic Patent References:
| JP4270488A | ||||
| JP387988A |
Attorney, Agent or Firm:
Kazuhide Okada
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