Title:
POSITION PULSE CORRECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS54138975
Kind Code:
A
Abstract:
PURPOSE:To present a position pulse correcting circuit with the corrected position not shifted and the detection error not produced. CONSTITUTION:A binary reversible counter 10 is to count up or down a count clock signal CI in accordance with the up/down signal U/D. A binary adder 11 processes an addition of ''1'' to an output of the binary counter 10 when in the counting up, with said output made passing by without any processing when in the counting down. A binary adder 12 processes an addition of AND output, between the signal inverted from output Gn to G1 of the binary adder 11 and the prescribed corrected value Zn to Z1, and the value applied to an input terminal An to A1, with its carry signal outputted as the count signal CO.
Inventors:
SHIROHIDE TAKASHI
Application Number:
JP4604578A
Publication Date:
October 27, 1979
Filing Date:
April 19, 1978
Export Citation:
Assignee:
KOMATSU MFG CO LTD
International Classes:
G05D3/12; G05D3/00; H03K21/00; H03K23/00; (IPC1-7): G05D3/00; H03K21/00