PURPOSE: To judge the positional relation between semiconductor chips by a position recognition pattern and to enhance a recognition accuracy by a method wherein recognition marks are respectively arranged at the corner parts of the chip by which the opposite angles of a quadrangular semiconductor chip are formed.
CONSTITUTION: Recognition marks 12a and 12b are respectively arranged at the corner parts, by which the opposite angles of a quadrangular semiconductor chip 11 are made, of the chip 11 and the marks 12a and 12b are formed into a quadrangular form and are arranged on the sides inner slightly from the outer peripheries L of the chip. An area with a feature is previously ready-stored in a memory as a reference pattern in a processing system 8, a position recognition pattern which is formed by the marks 12a and 12b of the chip 11 is read out by a camera 7 and the position recognition pattern detected by the processing system 8 is compared with the previously stored reference pattern. An area having most meeting points is recognized as a target pattern, the amount of the positional deviation of the center of the reference pattern from the center of the recognized pattern is read and the final wire bonding position is decided.
| JP5120751 | Bonding equipment |
| JP2001007144 | WIRE BONDING METHOD AND DEVICE |
| JPS5758326 | SEMICONDUCTOR DEVICE EMPLOYING CONDUCTIVE PASTE |
FUJIMOTO YUTAKA
ISHIKAWA KATSUMI
| JPS63185233U | 1988-11-29 | |||
| JPS5881938U | 1983-06-03 | |||
| JPS5741653U | 1982-03-06 |