Title:
電力増幅装置
Document Type and Number:
Japanese Patent JP7091555
Kind Code:
B2
Abstract:
A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.
Inventors:
Kazuhiko Ohashi
Masatoshi Uetani
Koki Yamamoto
Masatoshi Uetani
Koki Yamamoto
Application Number:
JP2021511514A
Publication Date:
June 27, 2022
Filing Date:
March 24, 2020
Export Citation:
Assignee:
Nuvoton Technology Japan Corporation
International Classes:
H03F3/213; H01L23/36; H03F1/30
Domestic Patent References:
| JP99054935A1 | ||||
| JP2007266539A | ||||
| JP2002344147A | ||||
| JP2001102483A | ||||
| JP2003008470A | ||||
| JP2014007323A |
Attorney, Agent or Firm:
Hiroi Arai
Teraya Eisaku
Shinichi Michizaka
Teraya Eisaku
Shinichi Michizaka
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