Title:
POWER ON CLEARING CIRCUIT
Document Type and Number:
Japanese Patent JP3700832
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a power on clearing circuit capable of completely stopping an abnormal operation of a signal processor occurring in the case of removing a panel.
SOLUTION: A delay of a power on clear signal is suppressed by taking an AND of an output inverted by an inverter 1 from an AND output of a panel upper part insertion or removal detection signal and a panel lower part insertion or removal detection signal indicating an insertion or a removal of upper and lower parts of a panel when the panel is removed and the power on clear signal having a delay caused by a time constant and output from a voltage monitoring circuit 2. The signal processor 4 is cleared by the power on clear signal for suppressing the delay.
Inventors:
Dr. Hashimoto
Application Number:
JP2000171373A
Publication Date:
September 28, 2005
Filing Date:
June 08, 2000
Export Citation:
Assignee:
nec Engineering Co., Ltd.
International Classes:
H03K17/22; (IPC1-7): H03K17/22
Domestic Patent References:
| JP59138925U | ||||
| JP6110583A | ||||
| JP61193220A | ||||
| JP5036943U |
Attorney, Agent or Firm:
▲柳▼川 信
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