Title:
パワーコンバータ回路及び方法
Document Type and Number:
Japanese Patent JP4599167
Kind Code:
B2
Abstract:
A system is disclosed for controlling a plurality of pulse-width-modulated switching power converters. The system includes a sample and hold circuit which is configured to receive information at time-separated intervals. The information the sample and hold circuit receives includes information which is indicative of the performance of the power converters. In some embodiments, the sample and hold circuit takes samples of data from each of the switching power converters and provides information to an analog to digital conversion circuit coupled to the sample and hold circuit. In one embodiment, the plurality of pulse-width-modulated switching power are configured to independently provide power to unrelated loads.
Inventors:
Kernahan, Kent
Fraser, David, F.
Loan, jack
Fraser, David, F.
Loan, jack
Application Number:
JP2004553795A
Publication Date:
December 15, 2010
Filing Date:
November 13, 2003
Export Citation:
Assignee:
EXAR CORPORATION
International Classes:
H02M3/155; G05F3/26; H02J7/00; H02M1/084; H02M3/156; H02M3/157; H02M3/158; H03M5/08
Domestic Patent References:
| JP2003528553A | ||||
| JP7222448A | ||||
| JP2001078370A |
Foreign References:
| WO2002080343A1 |
Other References:
High performance predictive dead-beat digital controller for DC power supplies,Bibian, S.; Jin, H.;,Applied Power Electronics Conference and Exposition, 2001. APEC 2001. Sixteenth Annual IEEE,米国,APEC,2001年 3月 4日,Volume 1, 4-8 March 2001,67 - 73
Attorney, Agent or Firm:
Mieko Kashihara