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Title:
POWER FAILURE PROTECTION SYSTEM FOR DYNAMIC RAM
Document Type and Number:
Japanese Patent JPH03194793
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption for power backup by providing a control switching means, which refreshes and controls a dynamic RAM by a signal generating circuit in the case of a power failure of a device power source, and a battery which supplies the backup power to the dynamic RAM and the control switching means.

CONSTITUTION: A signal generating circuit 4 is provided which generates a refresh signal to refresh a DRAM 2, and the DRAM 2 is controlled by a private DRAM controller 3 if the device power source is normal, and the DRAM 2 is refreshed and controlled by the signal generating circuit 4 when a power failure occurs in the device power source. A control switching circuit 5 and the DRAM 2 are backed up with a battery B. Consequently, the refresh control is performed by the signal generating circuit 4 of small current consumption but the DRAM controller 3 of large current consumption is not used at the time of a power failure. Thus, the power consumption for power backup is reduced.


Inventors:
UKEGAWA TAKESHI
Application Number:
JP33259489A
Publication Date:
August 26, 1991
Filing Date:
December 25, 1989
Export Citation:
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Assignee:
RICOH KK
International Classes:
G11C11/405; G11C11/401; (IPC1-7): G11C11/405
Attorney, Agent or Firm:
Makoto Monda