Title:
Power supply impedance optimization device
Document Type and Number:
Japanese Patent JP6220681
Kind Code:
B2
Inventors:
Koji Kawahara
Application Number:
JP2014005810A
Publication Date:
October 25, 2017
Filing Date:
January 16, 2014
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
H01L21/822; H01L27/04
Domestic Patent References:
| JP2012190862A | ||||
| JP2009099718A | ||||
| JP2008076356A | ||||
| JP2009288040A | ||||
| JP2008524951A | ||||
| JP2010258536A |
Foreign References:
| US20060192300 |
Attorney, Agent or Firm:
Nozomi Watanabe
Haruko Sanwa
Haruko Sanwa
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