To suppress power supply voltage rise under a light load.
A chopper circuit CH1. comprising a capacitor C5, an inductance L2 and a switching element Q3 is connected in parallel with a pseudo-power supply, i.e., a capacitor C1, between the pulsating output terminals of a rectifier DB. The switching element Q3 comprises an FET including a parasitic diode Da and it is turned on/off by a control circuit CNT. for driving the main switching elements Q1, Q2 in an inverter circuit INV1. A circuit can be selected depending on the operation mode of the inverter circuit INV1 (preheating mode and lighting mode for a discharge lamp La) by turning the switching element Q3 on/off through the control circuit CNT1. According to the arrangement, supply voltage to the inverter circuit INV1 can be prevented from increasing under a light load while suppressing stress on the main switching elements Q1, Q2.
NISHIMOTO KAZUHIRO
HAMAMOTO KATSUNOBU
