Title:
POWER VOLTAGE DROPPING CIRCUIT AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH09198151
Kind Code:
A
Abstract:
To reduce power consumption by reducing power consumption when a load circuit is in a stand-by mode in a power voltage dropping circuit making power source voltage supplied from outside drop.
At the time of the stand-by mode, a reference voltage generation circuit 31 is made inactive to prevent a power source current from flowing and also in an operation amplifier 53, the feedback control operation of dropping voltage VOUT is stopped to prevent a power source current necessary for feedback control operation from flowing. In addition, a pMOS transistor 18 is turned off and dropping voltage VOUT is obtained by a voltage dividing circuit consisting of resistors 23, 20 and 21 to secure data holding operation in the loading circuit 12.
Inventors:
NUNOKAWA HIDEO
Application Number:
JP787596A
Publication Date:
July 31, 1997
Filing Date:
January 19, 1996
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L27/04; G05F1/46; G05F1/56; G05F3/24; G11C11/407; H01L21/822; H01L21/8238; H01L27/092; H01L29/417; (IPC1-7): G05F3/24; G05F1/56; H01L21/822; H01L21/8238; H01L27/04; H01L27/092
Attorney, Agent or Firm:
Tetsuo Hirado
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