Title:
PRE-CODER
Document Type and Number:
Japanese Patent JP3319287
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a pre-coder which can perform pre-coding so that the same value is not continued for several bits or more (especially, the same value is not continued in an important part such as ID or the like) even if the same value is continued for the prescribed bits or more in input data.
SOLUTION: An inverter 12 converts input data to be recorded or transferred into an inverse logic value. An adder 2 adds output data of the inverter to output data of a delay circuit 5, and outputs pre-coded data to an output terminal 6 and the delay circuit 5 through a changeover switch 3. The changeover switch 3 switches and outputs a synchronizing signal Sync from an input terminal 4. The delay circuit 5 delays pre-coded output data by a prescribed time and outputs it to the adder 2. Even when 16 bits of input data are all '0' and a value of the last two bits of the synchronizing signal Sync is set to '00', a pre-code output in which the same value is not continued beyond two bits can be obtained.
Inventors:
Seiji Higurashi
Youichi Zenno
Youichi Zenno
Application Number:
JP15534196A
Publication Date:
August 26, 2002
Filing Date:
June 17, 1996
Export Citation:
Assignee:
Victor Company of Japan Ltd.
International Classes:
G11B20/10; G11B20/14; H03M5/14; H03M13/23; H04L25/49; (IPC1-7): G11B20/14; H03M5/14; H03M13/23; H04L25/49
Domestic Patent References:
| JP6187737A |
Attorney, Agent or Firm:
Kaneyuki Matsuura