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Title:
PREPARATION OF LSI TEST PATTERN
Document Type and Number:
Japanese Patent JPS59187276
Kind Code:
A
Abstract:

PURPOSE: To enable the preparation of patterns without requiring labors by executing the exclusive OR operation between a defective pattern of a fail memory and a test pattern at the address determined to be defective to make a test pattern regarding the result as accepted pattern.

CONSTITUTION: When a defective address and a defective pattern are found, an exclusive OR operation is executed with an LSI tester T between the defective pattern of a fail memory 7 and a test pattern at the (n) address corresponding to the defective address of a pattern memory 6 to obtain an accepted pattern the same as the pattern from a CPU1 and the accepted pattern is written into the (n) address of the memory 6. Such an operation is executed until the defective address disappears to complete the flow of preparing a test pattern. Thus, a test pattern for the CPU1 can be prepared on the memory. The test pattern thus prepared is stored in a disc device or the like and used to test a device to be measured.


Inventors:
OKUMURA KENZOU
MASUI KATSUHIRO
Application Number:
JP6194183A
Publication Date:
October 24, 1984
Filing Date:
April 07, 1983
Export Citation:
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Assignee:
SHARP KK
International Classes:
G06F11/22; G06F11/263; G01R31/28; (IPC1-7): G01R31/28; G06F11/22
Attorney, Agent or Firm:
Takeshi Sugiyama



 
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