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Title:
PREPARATION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5648165
Kind Code:
A
Abstract:

PURPOSE: To obtain a high resistance part of high resistance value accuracy by forming a high melting point metal layer selectively on a polycrystalline silicon layer whose resistivity is made to a desired high resistance value and forming a wiring pattern using the exposed part of the silicon layer for the high resistance part.

CONSTITUTION: On a P type silicon substrate 10, a thick field silica film 11 is formed, and on the surface of the substrate 10 surrounded by the film, a thin gate silica film 12 is coated, and here, an opening for drain contact is made, and nondoped polycrystalline silicon is stacked over the entire surface so that a desired high resistivity part R may be obtained. Next, covering the region where the resistor part R has been formed with a resist mask, a metal layer of Mo, etc., is coated over the entire surface, and by patterning the layer and the polycrystalline silicon, a polycrystalline silicon gate layer 13 and a molibdenum gate electrode 15 are formed on the film 12. At the same time, molibdenum wiring layers 16 and 17 are remained except on the high resistivity part R, and in the substrate 10 on both sides of the layer 13, N+ type source and drain regions 19 and 20 are diffusion formed, and also an N+ type contact region 21 neighboring the region 20 is formed by ion implantation.


Inventors:
NAGAI AKIRA
YAMAMOTO AKIRA
Application Number:
JP12409879A
Publication Date:
May 01, 1981
Filing Date:
September 28, 1979
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/04; H01L21/3205; H01L21/822; H01L23/52; H01L27/06; H01L29/78; (IPC1-7): H01L21/88; H01L27/04; H01L29/78