Title:
PREPARATION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58151032
Kind Code:
A
Abstract:
PURPOSE:To eliminate irregularity in the amount of glass to be filled and enhance reliability of high voltage resistance element by providing a recess at the surface in view of protecting the P-N junction formed on a semiconductor substrate, previously diffusing impurity selectively in the region where a recess is to be formed at the time of filling herein a glass material and by etching such region. CONSTITUTION:An SiO2 layer 6 is deposited on a semiconductor substrate 1, a specified opening is bored, a first region 2 and a second region 3 are formed by diffusion, a P-N junction is formed between these and the substrate 1. Then, a shallow recess is formed at the surface in order to protect this P-N junction and it is filled with a glass material in the following manner. Namely, an SiO2 layer 6 is renewed and an opening is newly bored and a shallow third region 12 is formed by diffusion while the regions 2 and 3 are included. When the region 12 is etched thereby, a shallow recess 14 having flat bottom surface can be obtained and there occurs no irregularity in the glass material to be filled.
Inventors:
HIDESHIMA MAKOTO
MURAMOTO KENICHI
SAKURAI KIYOSHI
MURAMOTO KENICHI
SAKURAI KIYOSHI
Application Number:
JP3174182A
Publication Date:
September 08, 1983
Filing Date:
March 02, 1982
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/316; (IPC1-7): H01L21/316
Attorney, Agent or Firm:
Inoue Kazuo