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Title:
PREPARATION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58151057
Kind Code:
A
Abstract:

PURPOSE: To obtain a device having flat surface and less interface leak current through the formation of insulated land layers by implanting any of O, N and C to the epitaxial layer on an Si substrate with an insulating layer used as the mask.

CONSTITUTION: A single crystal Si 22 is epitaxially formed on a sapphire substrate 21, the O ion is implanted twice by changing an acceleration voltage with SiO2 23' used as the mask, thereby peak concentration of O can be obtained at the lower layer of the layer 22 and at the surface of substrate 21 and concentration becomes almost zero at the intermediate portion of layer 22. When, an element is processed at 1,000°C under the ambient N2, an SiO2 film 24 is formed at the lower layer portion. Since O ion is implanted at the entire part of the peripheral layer 22, an SiO2 film 25 can be obtained at the entire part. The mask 23' is removed, and a gate oxide film 28, poly-Si gate electrode 27, n+ type source, drain 29, 30, and SiO2 film 31, electrode 32 are formed sequentially. A self-diffusion of Al from the substrate 21 is rejected because of existence of the SiO2 film 24 and thermal oxidation time is drastically curtailed. Thereby, lateral diffusion of O2 during thermal oxidation is suppressed, leak current is reduced and moreover the surface becomes flat.


Inventors:
NAKAHARA MORIYA
Application Number:
JP3274082A
Publication Date:
September 08, 1983
Filing Date:
March 02, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L29/786; H01L21/265; H01L21/3205; H01L21/86; H01L27/12; H01L29/78; (IPC1-7): H01L21/265; H01L21/86; H01L21/88; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue



 
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