Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PREPARATION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5853858
Kind Code:
A
Abstract:

PURPOSE: To prevent contamination, external diffusion during thermal diffusion and lower the generation rate of crystal defect by leaving a thin thermal oxide film on the region where the P well may be formed.

CONSTITUTION: An N type Si substrate 11 is oxidized under the moistened condition in order to form an SiO2 film, a resist mask 13 is coated and ions are implanted. Thereafter, a P well 14 is formed under the SiO2 film 12. Next, the SiO2 film 12 is etched until the film thickness becomes about 500°C and the mask 13 is removed. The P well 14 is thermally diffused for about 15hr in the dried O2+N2 ambient at 1,200°C and then for about 15hr in the dried N2 ambient at 1,200°C. Thus, the P well 15 is completed. At this time, the region where the P well may be formed is also oxidized, forming a step between this region and P channel region. This step can be used as the alignment standard of the next photo-etching process. According to this structure, generation rate of crystal defect in the well region is lowered and yield and reliability of product can be improved.


Inventors:
BABA ISAO
KONDOU TAKEO
SAITOU YASUYUKI
KOBAYASHI KIYOSHI
ADACHI NOBUHIRO
Application Number:
JP15265781A
Publication Date:
March 30, 1983
Filing Date:
September 26, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue