To provide a prescaler circuit capable of stably performing frequency division without being affected by a frequency division ratio N and the delay of a circuit at the time of the frequency division, preventing the generation of spurious signal other than target signals as the output signals and improving a C/N.

This circuit is provided with a 1/2 frequency divider compose of a dynamic type flip-flop 30 and a first inverte 11 for frequency dividing input clocks into 1/2, a second inverter 12 for inverting the output signals of the 1/2 frequency divider and two NOR circuits for turning the output signal of the 1/2 frequency divider and the output signal of the second inverter 12 to one input signal and turning the input clock to the other input signal. The output signals of the respective NOR circuits are selectively outputted as frequency division signals in response to the level change of external control signals (m) by a signal selection circuit 31 and the timing of fetching the level change of the external control signals (m) by the signal selection circuit 31 is decided by the output signals of the signal selection circuit 31 by a timing gate 32 added to the signal selection circuit 31.