Title:
PRIORITIZED INFORMATION PACKET SWITCHING SYSTEM
Document Type and Number:
Japanese Patent JPH021663
Kind Code:
A
Abstract:
PURPOSE: To improve an efficiency of a buffer memory by combining a write control for a buffer memory and a package reading processing with a sematic priority. CONSTITUTION: A label conversion memory MC generates a new label (j) as one operation and generates a stand-by file selection signal (s) in a switching circuit ACE as the other operation. The memory MC supplies two bits p1, p2 to the circuit ACE. When the bit p1 is '0', a packet has sematic priority, and when the bit p1 is '1', the packet does not have the priority. When the bit p2 is '0', the packet has timewise priority, and when the bit p2 is '1', the priority is not included. When a label converted by the memory MC is a non-free packet label, a bit '1' is impressed to a buffer memory MP, and in the other case, a bit '0' is impressed.
Inventors:
KUANKUI JIYANNPOORU
RESUPANIYOORU ARUBEERU
KERUBERUNE JIYATSUKU IBUON
RESUPANIYOORU ARUBEERU
KERUBERUNE JIYATSUKU IBUON
Application Number:
JP17684488A
Publication Date:
January 05, 1990
Filing Date:
July 14, 1988
Export Citation:
Assignee:
FRANCE ETAT
International Classes:
H04L12/56; (IPC1-7): H04L11/20; H04L12/56
Domestic Patent References:
| JPS59135994A | 1984-08-04 | |||
| JPS57125439A | 1982-08-04 |
Attorney, Agent or Firm:
Makio Chonan (1 person outside)
Next Patent: JPH021664