Title:
PROCESS FOR MANUFACTURING INTEGRATED CIRCUIT HAVING DUAL DAMASCENE STRUCTURE AND CAPACITOR
Document Type and Number:
Japanese Patent JP2002043433
Kind Code:
A
Abstract:
To provide a side-wall capacitor in an integrated circuit including a dual damascene structure.
A process for forming the dual damascene structure and the capacitor includes forming of a stack having an insulating layer and a stopping layer (steps 10-25). The stack is pattern-formed (step 30) so as to form an opening part which is used in order to form the side-wall capacitor (step 35) when a via or a groove of the dual damascene structure is formed. As a result, the process for manufacturing the side-wall capacitor can be integrated with the dual damascene process without adding a further mask or etching process.
Inventors:
CHITTIPEDDI SAILESH
Application Number:
JP2001181366A
Publication Date:
February 08, 2002
Filing Date:
June 15, 2001
Export Citation:
Assignee:
AGERE SYST GUARDIAN CORP
International Classes:
H01L21/768; H01L21/02; H01L21/3205; H01L21/822; H01L23/52; H01L27/04; (IPC1-7): H01L21/822; H01L21/3205; H01L21/768; H01L27/04
Attorney, Agent or Firm:
Masao Okabe (11 others)