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Title:
PROCESSING METHOD IN RECOVERY MODE OF POWER SUPPLY INTERRUPTION FOR MICROCOMPUTER
Document Type and Number:
Japanese Patent JPS5816352
Kind Code:
A
Abstract:

PURPOSE: To avoid an error of process, by starting the execution at the address following the address which is executed right before the interruption of a power supply when the interruption of the power supply is recovered.

CONSTITUTION: A program is assorted into a processing routine that has no problem regardless of the interruption of a power supply and a processing routine that has a process error, etc. when the power supply is interrupted. When the power supply is interrupted, a flag Fo is set up at the head address of a program routine that has a data process error, etc. and then the flag Fo is concelled in the final address. Then a detection signal Sb is delivered to a CPU1 when the interruption of the power supply is caused or recovered. Thus the flag Fo is discriminated. In such way, the step following the step which is executed right before the power supply is interrupted when the interruption of the power supply is recovered.


Inventors:
IKEKITA MINORU
Application Number:
JP11472181A
Publication Date:
January 31, 1983
Filing Date:
July 21, 1981
Export Citation:
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Assignee:
ISHIDA SCALE MFG CO LTD
International Classes:
G06F1/30; G06F11/00; (IPC1-7): G06F1/00; G06F11/00
Domestic Patent References:
JP39024502A
JPS4918441A1974-02-18
JPS554651A1980-01-14
Attorney, Agent or Firm:
Toyoaki Fukui



 
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