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Title:
PROCESSING SYSTEM FOR ANALOG DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JPS55164976
Kind Code:
A
Abstract:

PURPOSE: To enable to add the correction to the A/D conversion only with a simple circuit, by adding the addition and subtraction for control signal at sampling mode for input analog signal, in charge re-distribution system.

CONSTITUTION: The input analog signal Ain is charged to the capacitor group C1WCn during the time when the sampling switch 11 is ON. During this first sampling period, one switch among the switches 13-1W13-n is connected to the reference voltage source + Vref or - Vref. Further, when the output of the comparator 12 is 1, the logic circuit 15 connects the contact of the switch 14 to - Vref via the switch decoder 17, and when 0, to + Vref. Accordingly, during the sampling period, with the operation of one switch among the switches 13-1W13-n and the switch 14 corresponding to the control digital signal CD, the addition and subtraction of the control analog signal specified with the signal CD to the signal Ain is made and the digital signal Dowt can be obtained with correction added.


Inventors:
OOHATA MICHINOBU
MATSUMURA TOSHIHIKO
YAMAZAWA MASAO
Application Number:
JP7064879A
Publication Date:
December 23, 1980
Filing Date:
June 07, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06J1/00; (IPC1-7): G06J1/00



 
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