PURPOSE: To calculate accurate load capacity by recognizing the sort of a signal line by the recorded result of a signal change in a logic circuit which is formed by event driven type logical simulation.

CONSTITUTION: A signal line including the same signal as a signal change defined as a clock signal in plural periods is recognized as a clock signal line by using the recorded result 23 of a signal change in the logic circuit which is formed by the event driven type logical simulation and distinguished from other general signal lines. A load capacity limit value 9 is calculated by respectively different references for the clock signal line and other general signal lines in the logic circuit. A control circuit (including a CPU) 2 controls the whole device and an output device 4 outputs a processed result.