PURPOSE: To obtain a prescribed S/N-to-error bit factor, by substituting the sampling time for the time variable of an operation equation to perform an operation of an obtained sampled value operation equation and then varying the discriminating state number of the sampled value operation equation, the process bit number and the process stage number of the optimum operation equation respectively.

CONSTITUTION: A sampled value data system SD1 is provided to a modulating circuit MOD of a modulator/demodulator to produce the carrier wave at the terminals C and S. The sampled value is multiplied by the outputs of LPFSL1 and SL2 through an A/D multiplier of the output side. Then the difference of results is obtained by a differential amplifier and then fed to a transmission line via a separating circuit DS. At the same time, the receiving signal is received at a demodulating circuit DME via a separating circuit DR and then multiplied by the demodulated carrier wave of the output of a sampled value data system SD2 through an A/D multiplier. This multiplied output is quantized by a D/A converter DA and via the LPFRL1 and RL2 to be applied to the system SD2. Then the timing of the sampling mode is detected. This timing is applied to a VCO to control the frequency. The synchronism is secured between the transmitter and receiver sides by means of the working clock of a terminal device TME.