PURPOSE: To improve the arithmetic ability of a byte or multi-byte operand while keeping the simplified single bit structure of a processor element by providing a serial shift register and a multiplexer at each processor element.

CONSTITUTION: Concerning processor arrangement for using SIMD architecture formed so that plural single bit processor elements PE can be provided with one operand at least in an arithmetic unit ALU, further, each processor element PE is provided with a multibyte serial shift register Z containing a data output concerning each byte position and a multiplexer Z-MUX formed for communicating data from any output selected out of outputs to the arithmetic unit ALU. Thus, high-level compatibility with an ordinary single bit arrangement is provided, various word lengths can be processed and shift ability can be improved.