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Title:
PROCESSOR SUB-SYSTEM TO BE USED FOR GENERAL COMPUTER ARCHITECTURE
Document Type and Number:
Japanese Patent JPH113313
Kind Code:
A
Abstract:

To obtain interchangeability with processor types in a wide range and to evade necessity of changing reference system architecture by executing conversion between a standardized bus interface for a host system and a specific bus interface for a processor.

A processor system is inserted into a slot of a computer system or stored in a printed circuit board card 200 to be inserted. The card 200 includes a processor sub-system having a processor 11 to be driven in accordance with a specific signal protocol different from a signal protocol for a system bus 101. A bus converter 15 is connected to the pin of the processor 11 and the standardized bus interface of the card 200 and connected also to the system bus 101. The converter 15 converts the signal protocol for the system bus 101 into the signal protocol for the processor sub-system and vice versa.


Inventors:
FISCH MATTHEW A
JACOBSON JR JAMES E
RHODEHAMEL MICHAEL W
Application Number:
JP17865397A
Publication Date:
January 06, 1999
Filing Date:
July 03, 1997
Export Citation:
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Assignee:
INTEL CORP
International Classes:
G06F13/38; G06F13/36; G06F13/40; G06F13/42; (IPC1-7): G06F13/36
Attorney, Agent or Firm:
山川 政樹



 
Next Patent: JPH0113314