Title:
PROCESSOR WITH BIT SLICE CONDITION, ITS PROGRAM AND ITS STORAGE MEDIUM
Document Type and Number:
Japanese Patent JP2002311828
Kind Code:
A
Abstract:
To branch a condition in a bit slice mounted device.
Vectors A and B are inputted which are obtained by respectively performing bit slice expression concerning the w elements a0 to aw-1 and the w elements b0 to bw-1 of an m-bit finite body GF(2m'). A logical product A and k obtained by A and data k being ≥w bits and also the logical product B and k obtained by B and k being the inversion of k are respectively obtained. The logical sum (k and A) or (k and B)=C is obtained. When ki is 1, a(i) obtains selected c(i) wherein C=(c(0) to c(m-1)). When ki is 0, b(i) obtains it.
Inventors:
KOBAYASHI TETSUTARO
HOSHINO FUMISATO
OGURO HIROAKI
HOSHINO FUMISATO
OGURO HIROAKI
Application Number:
JP2001115666A
Publication Date:
October 25, 2002
Filing Date:
April 13, 2001
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G09C1/00; (IPC1-7): G09C1/00
Attorney, Agent or Firm:
Kusano Taku (1 person outside)