PROCESSOR - SEIKO EPSON CORP

Title:

PROCESSOR

Document Type and Number:

Japanese Patent JP2000215050

Kind Code:

A

Abstract:

To execute a composite instruction on the hardware of a reduced instruction set computer by integrating subsets of more than one group into a final bucket having the maximum capacity of a specific number of native instructions and outputting subsets of native instructions of the final bucket on a host computer.

The processor consists of a main instruction buffer(MBUF) 204, an emulation instruction buffer(EBUF) 202, and a target buffer(TBUF) 206. Then subsets of at least two groups of native instructions are integrated into the final bucket having the maximum capacity of a specific number of native instructions to enable a host processor to output the subsets of the native instructions of the final bucket. Further, a specific number of native instructions are four native instructions and a stream of non-native instructions includes at least two non-native instructions.

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Inventors:

COON BRETT
MIYAYAMA YOSHIYUKI
NGUYEN LE TRONG
WANG JOHANNES

Application Number:

JP2000007261A

Publication Date:

August 04, 2000

Filing Date:

March 30, 1993

Export Citation:

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Assignee:

SEIKO EPSON CORP

International Classes:

C10G1/00; C10G17/02; G06F9/22; G06F9/30; G06F9/318; G06F9/38; G06F15/76; (IPC1-7): G06F9/30; G06F9/30; G06F9/38

Attorney, Agent or Firm:

Ryuyoshi Abe (7 outside)

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