Title:
PRODUCTION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3186421
Kind Code:
B2
Abstract:
PURPOSE: To provide a production process wherein the number of steps and cost can be reduced in the BiCMOS technology including DMOS.
CONSTITUTION: Ions of an acceptor are very shallowly implanted into the surface of a p-type well 5 to form a channel layer 8 and gate electrode 20 of poly-Si is formed on a gate isolation film 9 and local oxide film 7a. By the help of a bipolar transistor making process, the ion implantation is made to form a p-type base region 21 through the electrode 10 used as a mask, then side walls 25 are formed at both sides of the electrode 10 at high temp., utilizing the LDD structure forming step in the CMOS process, and the impurity is diffused to form a p-type base region 21 at the same time. An n+-type source region 26NS is formed by self-aligning through the walls 25 used as a mask.
Inventors:
Mutsumi Kitamura
Naoto Fujishima
Naoto Fujishima
Application Number:
JP9940994A
Publication Date:
July 11, 2001
Filing Date:
May 13, 1994
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L27/06; H01L21/336; H01L21/8249; H01L29/78; (IPC1-7): H01L21/8249; H01L27/06; H01L29/78
Domestic Patent References:
| JP2201963A | ||||
| JP5136359A |
Attorney, Agent or Firm:
Masaharu Shinobe