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Title:
PRODUCTION OF THIN-FILM TRANSISTORS ARRAY SUBSTRATE
Document Type and Number:
Japanese Patent JPH09230382
Kind Code:
A
Abstract:

To obtain a thin-film transistor(TFT) substrate free from bright point defects without changing production stages by providing the above process with a stage for providing TFT regions and regions covering at least light shielding patterns with a-Si and a stage for etching regions for etching away the residues of this a-Si.

First wiring groups 1 are formed of metallic films on a glass substrate. In this case, the light shielding patterns 2 are formed in the same stage. Next, an insulating film 9 and an a-Si film are continuously formed and the TFT part a-Si films 10 forming the TFTs are formed by plasma CVD, etc. Further, the films to allow the a-Si to remain are simultaneously formed. Next, a resist is applied therein and is subjected to exposing and developing in a PR stage for forming contact holes for connecting the first wiring groups 1 and the upper layer metal. The photoresist 11 is bored with slits for trenches for the purpose of cutting the a-Si layer. This substrate is etched by a drying etching device.


Inventors:
WATANABE TAKAHIKO
Application Number:
JP4104996A
Publication Date:
September 05, 1997
Filing Date:
February 28, 1996
Export Citation:
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Assignee:
NEC CORP
International Classes:
G02F1/136; G02F1/1368; H01L21/77; H01L21/84; H01L27/12; H01L29/786; G02F1/1335; (IPC1-7): G02F1/136; H01L29/786
Domestic Patent References:
JPH06138487A1994-05-20
JPH0695150A1994-04-08
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)