Title:
PROGRAM LOGICAL OPERATION METHOD FOR RELAY CONNECTION LOGICAL PROCESSING
Document Type and Number:
Japanese Patent JP2549487
Kind Code:
B2
Abstract:
PURPOSE: To attain a high speed processing by unnecessitating a data reference procedure processing such as address calculation, data meaning judgement, etc., by executing logical discrimination by operating a logical operation program by preparing the dedicated logical operation program.
CONSTITUTION: In an electronic interlocking device, e.g. relay schematics data 1 of a relay interlocking device is developed to a Boolean algebra logical expression 2, the dedicated logical operation program 10 is prepared from the Boolean algebra logical expression 2, the prepared logical operation program 10 is mounted to ROM, etc., of a computer 5 such as the electronic interlocking device, etc., and the logical operation program 10 is operated to execute arithmetic processing so as to make the electronic interlocking device, etc., execute the same logical operation as relay schematics. Namely, the Boolean algebra logical expression is not converted to logical operation constant data but the dedicated logical operation program 10 is prepared from it. Logical operation itself by the logical operation program 10 is actually not logical operation but only executes the 0/1 discrimination of data.
Inventors:
MUNEKATA KOICHIRO
TAKAHASHI KUNITSUGU
SUGIMORI AKIHIKO
TAKAHASHI KUNITSUGU
SUGIMORI AKIHIKO
Application Number:
JP23929692A
Publication Date:
October 30, 1996
Filing Date:
September 08, 1992
Export Citation:
Assignee:
DAIDO SHINGO
International Classes:
B61L19/00; B61L29/00; G05B19/02; G06F17/50; G08B23/00; G08B25/00; (IPC1-7): G05B19/02; B61L19/00; B61L29/00; G06F17/50
Domestic Patent References:
| JP467206A |
Attorney, Agent or Firm:
Morio Sada (1 outside)