PURPOSE: To increase the speed of instruction cycle and also to eliminate the need to allot program instructions to a program memory, by previously dividing the program memory into two odd-address and even-address areas.
CONSTITUTION: For example, the current execution address is set in address register 340 as "A" to send output signal 340 and displacement 202S in the instruction cycle when the current execution address is "A" is written as "B", addition result 310S of adder 310 should invariably be odd and addition result 320S of adder 320 should be even. Therefore, access to an odd address of a program instruction stored in program memory 410 is attained and access to an even address of a program instruction stored in program memory 420 is attained. Once flag 100S is determined, the execution address of the next instruction cycle can be set to A+B or A+B+1 at any time.
IKEDA HIROKI
JPS5098256A | 1975-08-05 | |||
JPS4716045A | 1972-08-29 |