PURPOSE: To decrease memory capacity by switching a stack pointer to an interruptive process side when the interruptive process is generated, and reloading a saved stack on the basis of data stored in a program counter and a stack register when the interruptive process ends.

CONSTITUTION: This structure is provided with the stack register Px together with a stack Dr for an interruptive process side, and which stack is saved in a CPU register set Cr is stored. For example, when an interruptive process is performed while a task 1 is executed, the CPU contents executed by the task 1 are saved in the CPU register set Cr. At this time, the saving of the current task 1 in the CPU register set Cr is stored in the stack register Px, and the break point of the task is stored in a return P counter B1. Once the interruption ends, the process is restarted at the specific point of the task 1 according to the stack register Px and P counter B1.