Title:
PROGRAMMABLE INTEGRATED LOGIC DEVICE
Document Type and Number:
Japanese Patent JP2934149
Kind Code:
B2
Abstract:
PURPOSE: To provide a programmable logic device which can be programmed at a very high speed.
CONSTITUTION: A programmable integrated logic device is composed of a programmable array containing a plurality of input lines and a plurality of product term lines, a device terminal, a tri-state output driver provided with an input connected to the subset of the product term lines and an output connected to the device terminal, a digital multiplexer 140 provided with at least two input terminals and one output terminal, and a means which controls the multiplexer 140 for selecting one of product term signals to the output diver and preset logic signals as a control logic signal for transmission.
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Inventors:
JON II TAANAA
DEIBITSUDO ERU RATORIIJI
DEIBITSUDO ERU RATORIIJI
Application Number:
JP8092094A
Publication Date:
August 16, 1999
Filing Date:
March 28, 1994
Export Citation:
Assignee:
RATEISU SEMIKONDAKUTAA CORP
International Classes:
G01R31/3185; G11C16/02; G11C16/04; G11C17/00; H01L21/82; H01L21/8246; H01L21/8247; H01L27/10; H01L27/112; H01L29/788; H01L29/792; H03K19/173; H03K19/177; (IPC1-7): H03K19/177; G11C16/04; H01L21/82
Domestic Patent References:
JP589434A | ||||
JP61502650A |
Attorney, Agent or Firm:
Youichi Oshima
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