PURPOSE: To realize an AND place for one input signal with one input signal line, to eliminate the need for an input decoder, and to compress an area almost to a half by charging a product item line that is the output line of the AND plane in advance, and using both a P-type transistor and an N-type transistor for the discharge of the line.

CONSTITUTION: The input signals x1 and x2 are inputted to the AND plane 5. The value of the product item line 3 is decided with an N-type pull-down transistor 9 inserted between the input signal line 1 of the AND plane 5 and the ground and a P-type pull-down transistor 10 inserted between the input signal line 2 and the ground. Also, the value of the product item line 4 is decided with a P-type pull-down transistor 11 inserted between the input signal line 1 of the AND plane 5 and the ground, and an N-type pull-down transistor 12 inserted between the input signal line 2 and the ground. The product item lines 3, 4 that are the output lines of the AND place are inputted to an OR plane, and output signals z1-z2 can be decided.