PURPOSE: To avoid the drop of the pulse width by constituting the circuit of first and second FF circuits operated by a rise and a fall of an input signal supplied to a clock terminal, respectively, and an exclusive OR circuit for supplying their outputs, at the time of propagating a minute pulse signal in the circuit constituted of a logic circuit.

CONSTITUTION: When an input signal has been supplied to clock terminals CK of the first and second D-type FF circuits 1, 2, only the pulse width of an output signal B of the circuit 2 of a signal A and B outputted from output terminals Q is delayed from the output signal A of the circuit 1. Thereafter, these signals A, B are supplied to an exclusive OR circuit 3, from which a desired signal is outputted. According to such a constitution, even when the wiring capacitor between the output terminals of the circuits 1, 2 and the circuit 3 is large, the delay difference of two signals from the terminals Q is not varied and it takes only the time when they are supplied to the circuit 3, and the pulse width of the input signal is reproduced surely.