Title:
PROTECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH10173136
Kind Code:
A
Abstract:
To provide a protection circuit which greatly elevates the surge level, and does not deteriorate the element characteristics.
A bias circuit having an input terminal 1 connected to the gate of arm FET 10 and output terminal 2 connected to the source comprises a diode 5 and inductance 32 connected in series between the input terminal 1 and ground terminal, such that the RF component of an input signal to the input terminal 1 is inputted to the gate of the FET 10, while the surge frequency component flows to the ground terminal through the diode 5 and inductance 32, thus protecting the circuit from the surge voltage, without giving influence on the characteristics of the FET 10.
Inventors:
ISHII TETSUO
Application Number:
JP33567296A
Publication Date:
June 26, 1998
Filing Date:
December 16, 1996
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L27/04; H01L21/338; H01L21/822; H01L23/62; H01L29/812; H03F1/52; (IPC1-7): H01L27/04; H01L21/338; H01L21/822; H01L23/62; H01L29/812; H03F1/52
Attorney, Agent or Firm:
Kazuo Sato (3 others)