Title:
PSEUDO MULTIPORT MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3652909
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a pseudo multiport memory device which reads plural pieces of data from an unrelated address by using one or two mass memories.
SOLUTION: Shift registers 37 to 40 which respectively have the prescribed number of steps are parallelly arranged, pixel groups 35, 36, 33 and 34 read from a memory 32 in each clock CK are respectively stored in corresponding shift registers 39, 40, 37 and 38 in turn, each sift register also performs a shift operation in accordance with the CK, and desired pixels 16 to 19 are parallelly and simultaneously outputted to a PE array 45.
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Inventors:
Toshihiro Minami
Application Number:
JP4060099A
Publication Date:
May 25, 2005
Filing Date:
February 18, 1999
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F15/16; G06F12/00; G06F12/02; G06F12/04; G06F12/06; G06F15/167; G06F15/80; G06T1/60; H04N19/423; H04N19/50; H04N19/51; H04N19/57; (IPC1-7): G06F12/02; G06F12/00; G06F12/06; G06T1/60; H04N7/32
Domestic Patent References:
| JP4333938A | ||||
| JP9502818A | ||||
| JP5266056A | ||||
| JP10116226A |
Attorney, Agent or Firm:
Masaki Yamakawa
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