Title:
PULSE GENERATING CIRCUIT AND RECORDING MEDIUM DRIVER UTILIZING SAME
Document Type and Number:
Japanese Patent JPH05129940
Kind Code:
A
Abstract:
PURPOSE: To constitute a PLL circuit without using a capacitor, a crystal and a voltage controlled oscillator, etc.
CONSTITUTION: The period of a regenerated horizontal synchronizing signal inputted by a period counter 12 is measured and a mean value arithmetic operation circuit 14 calculates the means value and stores the result to a mean period register 15. A window control circuit 17 monitors a mean period stored in the means period register 15 to decide whether or not the period is within the range of a prescribed window. A window control circuit 18 controls the period of an FH pulse outputted by an FH counter 21 corresponding to the result of decision of the window control circuit 17.
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Inventors:
YAMASHITA NORIYUKI
Application Number:
JP32133091A
Publication Date:
May 25, 1993
Filing Date:
November 08, 1991
Export Citation:
Assignee:
SONY CORP
International Classes:
H03L7/06; (IPC1-7): H03L7/06
Attorney, Agent or Firm:
Yoshio Inamoto