PURPOSE: To eliminate the need for any gate IC by extracting a load pulse, that is, a pulse having a pulse width corresponding to one period of a reference pulse at each period being a multiple of 4 of a period of a reference pulse.

CONSTITUTION: An output terminal Qe of a flip-flop circuit 5 being a phase adjustment means and an output terminal Qa of a flip-flop circuit 1 being a pulse output means are connected to form a so-called wired OR. Thus, a load pulse PSe, that is, a negative pulse with a pulse width corresponding to one period of the reference pulse CL is extracted from the output terminal Qe of the flip-flop circuit 5 at each a period being 4 times the period of the reference pulse CL. In other words, the load pulse is easily generated by having only to connect the pulse output means and each output terminal of the phase adjustment means. Thus, no gate IC is required and no gate delay is caused.