PURPOSE: To make a signal difficult to be influenced by the variation of power supply by providing a digital delay circuit, and shortening delay time due to delay in an analog way by delaying it previously in digital way when the whole delay time is long.

CONSTITUTION: According to the pulse of a set input signal 22, 0 is set in a half frequency division circuit 3, and a mixing circuit 1 is OR-mixed together with an input signal 21, and outputs a mixed signal 23. Next, the digital delay circuit 4 delays the leading edge of this mixed signal by set delay time tD1, and outputs a digitally delayed signal 26. Further, an analog delay circuit 2 delays the leading edge of this digitally delayed signal 26 by the set delay time tD2, and outputs an analogically delayed signal 24. Finally, the half fre quency division circuit 3 outputs a frequency divided output signal 25 to change at the leading edge of this analogically delayed signal 24. Thus, even when the delay time tD is long, the signal codes difficult to be influenced by the variation of the power supply.