To extend the input pulse width, to reduce the power of SRAM, to secure the generation timing of a pulse and to prevent malfunctions by providing a pulse width extending circuit.

When an inverted input signal Tin, whose pulse width is T1 is inputted to a pulse width extending circuit 1, a signal delayed by delay time d1 by a delay circuit 4 and Tin are logic-operated in a logic gate 5. Then, the output signal Tout of T1+d1 is obtained. At that time, Tout can be extended twice as much as input pulse width T1. In such a case, T1-d1 becomes the operation margin of the pulse width extending circuit 1. Thus, the operation margin can sufficiently be obtained by extending pulse width and newly generating pulse width. Then, the non-active periods of a word line and a sense circuit are prolonged during a write recovery period in SEAM, and the power of SRAM can be reduced. The operation margin can be secured adequately, even if the pulse width is enlarged, and malfunction due to the fluctuation of power voltage and so on can be prevented.