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Title:
PULSE SIGNAL DELIVER CIRCUIT
Document Type and Number:
Japanese Patent JPS63194413
Kind Code:
A
Abstract:

PURPOSE: To realize the compression of a circuit scale and the reduction of a price and to easily perform the successive and variable adjustment of the amplitude of an output pulse, by obtaining a pulse output from the secondary side output terminal of a transformer, by connecting the output of a logic IC to the anode of a first diode and the one end of a variable resistor, and connecting the other end of the variable resistor to the anode of a second diode.

CONSTITUTION: A transistor 2 is turned ON when the logic IC6 is set at an 'H' level, and goes to an OFF state when it is set at an 'L' level, and to the primary side of the transformer 1, a collector voltage at respective state is inputted, and at the secondary side output, the output pulse to be sent to a transmission line appears. And potential V1 at a point B is increased when the value of the variable resistor 8 is set at a large value, then, the amplitude of the output pulse is decreased. Also, the potential is decreased when that of the variable resistor 8 is set at a small value, and also, the amplitude of the output pulse is increased. Thus, since the amplitude of the output pulse can be adjusted successively by adjusting the variable resistor 8, it is possible to make an ATT circuit being provided at the secondary side of the transformer in a conventional circuit unnecessary.


Inventors:
HIRAGA MASATOMI
Application Number:
JP2773987A
Publication Date:
August 11, 1988
Filing Date:
February 09, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L25/02; H03K17/04; H03K17/60; H03K19/00; H03K19/0175; (IPC1-7): H03K17/04; H03K17/60; H03K19/00; H04L25/02
Domestic Patent References:
JPS5665527A1981-06-03
Attorney, Agent or Firm:
Naoki Kyomoto (1 person outside)



 
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