Title:
PULSE SWALLOW SYSTEM VARIABLE FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JP3260169
Kind Code:
B2
Abstract:
PURPOSE: To provide a pulse swallow system variable frequency divider which does not fall into an abnormal state at the time of power source supply and can compose the PLL system of a quick and stable operation.
CONSTITUTION: The divider is provided with a prescaler 1 dividing an input signal by either dividing rate of two kinds in accordance with a control signal, a 6-bit counter 2 and a 3-bit counter 4 respectively operating in synchronizing with the output of the prescaler 1 and a mode control circuit 5 giving the control signal to the prescaler 1 in accordance with the carry output of both counters 2 and 4. In a logical circuit 6 for providing dividing rate data to be loaded to both counters 2 and 4 by setting a signal obtained by exending the pulse width of the carry output of the 6-bit counter 2 to be an operation clock, a set input terminal is provided for temporarily and asynchronously setting a highest-order bit 68 of an output flip flop for the 6-bit counter which is normally set to be Low to be High at the time of power source supply.
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Inventors:
Masaaki Kano
Masakatsu Maruyama
Masakatsu Maruyama
Application Number:
JP22373492A
Publication Date:
February 25, 2002
Filing Date:
August 24, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H03K21/40; H03K23/64; H03L7/08; H03L7/199; (IPC1-7): H03K23/64; H03L7/199
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)